circuit note cn - 017 4 circuit designs using analog devices products apply these product pairings quickly and with confidence. for more information and/or support c all 1 -800- analogd (1 -800- 262 - 5643) or visit www.analog.com/circuit . devices connected /referenced adf4156 6 ghz fractional - n pll ADF5001 18 ghz divide -by - 4 prescaler op184 single - supply , rail -to - rail input/output operational amplifier low noise , 12 ghz , microwave f ractional - n phase - locked loop ( pll ) u sing an a ctive l oop f ilter and rf prescaler rev. a circuits from the lab? circuits from analog devices have been designed and built by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tes ted and verified in a lab environment at room temperature. however, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable f or direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any circuits from the lab circuits. (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010- 2011 analog devices, inc. all rights reserved. circuit function and benefits th is circuit is a complete implementation of a low noise microwave fractional - n pll using the adf4156 as the core fractional - n pll device . the ADF5001 external prescaler is used to extend the frequency range of the pll up to 18 ghz. an ultra low noise op184 op amp with appropriate biasing and filtering is used to drive a microwave vco to implement a c omplete low noise pll at 12 ghz with a m easured integrated phase noise of 0.35 ps rms. this function is typically used to generate the local oscillator frequency (lo) for applications such as microwave point - to - point systems, test and measurement equipment , automotive radar , and military applications. circuit description a block diagram of the circuit is shown in figure 1 . a 12 ghz vco from synergy microwave corporation, the dxo11751220 - 5 , was chosen for this circuit, although any vco operating from 4 ghz to 18 ghz would also work, provided the loop filter is redesigned appropriately. as with the majority of microwave vcos, the synergy vco has a wide input tuning range of 0.5 v to 15 v, wh ich requires an active pll loop filter to interface between the lower voltage adf4156 charge pump (maximum output of 5.5 v) and the vco input. the op184 was chosen as the op amp for the active loop filter because of its excellent noise performance , as well as its input ADF5001 prescaler adf4156 pll synergy vco dxo11751220-5 09259-001 3.3v 3.3v vdd1 rfin rfout rfin a rfinb cpout rfout gnd vdd2 3.3v 3.3v a vdd 5v vcc dvdd 5v vp gnd gnd decoupling integr a ted op184 op am p 2.2v 1f 47k? 100? 8.2k ? 1.8nf 15v 47nf 1.8nf 330? 1.8nf 1k? vtune rfout 18? 37? 150? 150? 18? 18? 12ghz out active pl l loo p fi l ter, 30khz closed loo p bandwidth 15v 6db p ad figure 1 . low noise microwave fractional - n pll (simplified schematic : all connections and decoupling not shown)
cn - 017 4 circuit note rev. a | page 2 of 3 and output rail - to - rail operation. a low noise op amp is required because the op amp output noise will feed through to the rf output, shaped by the active filter response. input rail - to - rail operation is also a very important consideration for pll active filters as it allows the use of a single op amp supply. this is because the charge pump output (cpout) will start at 0 v on power - up, which can cause problems for op amps that do not have rail - to - rail input voltage ranges. this also allows the noninverting input of the op amp to be biased at a voltage above ground with built - in margin to any changes in the bias voltage due to resistor mismatch or temperature change. it is recommended to set the bias voltage level to approximately half the charge pump supply ( vp ) , as this meets both the input voltage range requirements with plenty of margin and gives best charge pump spur performance. measurements for this circuit note were taken with vp = 5 v and op amp common - mode bias = 2.2 v. to h e l p minimize any reference nois e feed - through , a large decoupling cap acitor of 1 f was placed close to the non inverting op amp input pin as shown in figure 1 . this cap acitor with the 47 k ? resistor forms an rc filter with a cut - off below 10 hz . l oop f ilter design the pll loop filter design was done using analog devices free simulation tool, adisimpll . this tool allows the design and simulation of several passive and active pll loop filter topologies and has a library of analog devices op amps built in, which include the important op amp specifications such as voltage and current noise, input offset and bias currents , and voltage supply range. t he simulation tool accurately predicts pll closed loop phase noise and is able to model the effect of op amp noise along with the noise of the other pll loop components . the adisimpll simulation design file for this circuit note can be found at www.analog.com/cn0174_adisimpll . an inverting topology with pre - filtering was chosen. p re - filtering is advisable so as not to overdrive the amplifier with the very short current pulses from the charge pump which c ould slew rate - limit the input voltage. when using the inverting topology , it is important to make sure that the pll ic allows the pfd polarity to be inverted , cancel ing out the op amps inversion , and driv ing the vco with the correct polarity. the adf4156 pll has this pd polarity option. setup and measurement the settings used for the circuit are given in table 1 . measured results are shown in figure 2 versus th e simulated performance as predicted by adisimpll. as can be seen the results agree quite well. the measured integrated phase noise is 0.35 ps rms. the measurement setup is shown in figure 3 . table 1. test measurement settings arameter value nit rf frequency 12 ghz adf4156 rf input frequency 3 ghz pll loop filter bandwidth 30 khz reference input frequency 100 mhz pfd frequency 25 mhz charge pump setting 5 ma pd polarity bit negative noise mode low noise the performance of this or any high speed circuit is highly dependent on proper pcb layout. this includes, but is not limited to , power supply bypassing, controlled impedance lines (where required) , component placement, signal routing, power and g round planes. ( see mt - 031 tutorial , mt - 101tutorial , and article, a practical guide to high - speed printed - circuit - board layou t , for more detailed information regarding pcb layout.) ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 100 100m 10m 1m 100k 10k 1k phase noise (dbc/hz) frequency offset from carrier (hz) 09259-002 adisimpll simulated phase noise measured phase noise figure 2 . measured vs. simulated phase noise performance of the 12 ghz pll common variations there are several active loop filter topologies available in adisimpll, using both inverting or non - inverting op amp configurations. the phase noise trade - offs can be investigated in adisimpll. the inverting topology allows you to obtain output voltages as low as the minimum output voltage of the op amp , which can be as low as 125 m v for the op184 . in contrast to the non - inverting topology where the output voltage is limited to the minimum charge pump voltage (0.5 v) multiplied by the non - inverting gain.
cn - 0174 circuit note rev. a | page 3 of 3 100mhz power supply 5v rfouta cpout vtune rfout rfoutb rfin 15v signal generator r&s sma100a spectrum analyzer [r&s fsup26] adf4156 board 09259-003 active filter board ADF5001 board synergy vco board 10mhz reference synchronization 2-way splitter zfrsc-183-s+ figure 3 . measurement circuit learn more adisimpll design file for cn - 0174 adisimpll design tool adisimpower desig n to o l ardizzoni , john. a practical guide to high- speed printed - circuit - board layout analog dialogue , 39- 09, september 2005. harney, austin. designing high - performance phase - locked loops with high voltage vcos analog dialogue , dec.2009. mt - 031 tutorial, grounding data converters and solving the mystery of agnd and dgnd , analog devices. mt - 086 tutor ia l , fundamentals of phase locked loops , analog devices . mt - 101 tutorial, decoupling techniques , analog devices. data sheets and evaluation boards adf415 6 data sheet adf4156 evaluation board adf500 1 data sheet ADF5001 evaluat ion board op18 4 data sheet revision history 3/11 rev. 0 to rev. a changes to figure 2 .......................................................................... 2 10/ 10 revision 0 initial version (continued from first page) circuits from the lab circuits are intended only for use with analog devices products and are the intellectual property of analog devices or its licensors. while you may use the circuits from the lab circuits in the design of your product, no other license is granted by implication or otherwise under any patent s or other intellectual property by application or use of the circuits from the lab circuits . information furnished by analog devices is believed to be a ccurate and reliable. however, circuits from the lab circuits are supplied "as is" and without warranti es of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninf ringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for any infring ements of patents or other rights of third parties that may result from their use. analog devices reserves the right to change any circuits from the lab circuits at any time without notice but is under no obligation to do so. ? 2010 - 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn09259 - 0 - 3/11(a)
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